16-bit CPU in Logism-Evolution

Collaborated in the design and implementation of a custom 16-bit CPU using Logisim-Evolution, incorporating key architectural components including an ALU (arithmetic + relational operations), register file, datapath, memory modules, and a micro-architected control unit. The processor executed a small instruction set through a sequenced Fetch–Decode–Execute cycle, coordinated by truth-table–driven control signals. Demonstrated the ability to integrate digital logic, combinational/sequential circuits, and memory interfacing into a functional computing system.